Testing in the integrated circuit (IC) industry is a process of device verification to ensure that an IC is functionally acceptable. The IC industry tests every IC prior to shipping to the customers. In a test process, there are many test methods available to catch various defects introduced from manufacturing processes. The test methods can be classified into two categories, functional testing and parametric testing. Each test method provides data on the functionalities and reliabilities of the IC.
Functional testing verifies that the IC meets expected performance and functionality. During the functional testing, the basic functional properties of the IC is invoked, e.g., storing data into a memory and reading the stored data from the memory, programming Field Programmable Gate Arrays (FPGAs) and invoking functionalities of the programmed FPGA, etc. Parametric testing is a verification of parametric structures within the IC. The parametric testing is utilized to collect data on the process variations and tolerances. Based on information gathered through the parametric testing, the IC's reliability is established. The parametric testing includes testing of resistance, capacitance or inductance of a parametric structure.
For the parametric testing, a parametric measurement unit (PMU) is used to test the structures. The PMU transfers a voltage into the IC and measures the current. The current is either being drawn or leaked from the PMU to the IC. In order to force a voltage into the IC, the voltage needs to be either ramped or de-ramped gradually to a certain level by the PMU before forcing the voltage into the IC. Ramping or de-ramping of a voltage incurs a significant amount of add-on test time. An example of a relatively high add-on test time occurs when a tester having a single PMU tests an IC having multiple parametric structures. The single PMU will be required to either ramp up or ramp down the voltage level to test each of the parametric structures. Such activity incurs high costs in part due to the high test time. Furthermore, as the IC devices are becoming larger in terms of size and complexity, the numbers of the structures in the ICs are increasing. Therefore, as each generation progresses, the cost to test the IC increases.
It is within this context that the embodiments described herein arise.